The present invention relates generally to semiconductor memory devices, and particularly to a dynamic random access memory (DAM) having a memory cell with buried word and body lines.
Dynamic random access memories (DRAMs) typically include an array of tacked or deep trench capacitors for storing data as charge. Memory cell access field-effect transistors (FETs) are provided for switchably accessing the charge storage nodes of these storage capacitors. DRAMS that are fabricated on bulk silicon substrates are susceptible to xe2x80x9csoft errorsxe2x80x9d resulting from alpha particles that stray from the environment or integrated circuit package. Such alpha particles penetrate the bulk silicon substrate, where they generate large numbers of minority charge carriers. These minority charge carriers are collected at reverse-biased pnxe2x88x92 junctions of the access FETs, where they perturb the data that is stored as charge on the storage capacitors. For immunity to such soft errors, large trench or stacked storage capacitors are required in bulk silicon DRAMs in order to store large quantities of charge. These capacitors constitute an estimated 30% of DRAM fabrication cost.
By contrast, DRAMs that are fabricated using semiconductor-on-insulator (SOI) substrates are more immune to soft errors. SOI substrates typically comprise a thin layer of active semiconductor, such as silicon, on an underlying insulating layer, such as silicon dioxide (SiO2). Memory cells are fabricated upon the thin active semiconductor layer. The number of minority charge carriers generated by a penetrating alpha particle decreases along with the available semiconductor volume. Since SOI substrates present less available semiconductor volume than bulk silicon substrates, fewer minority carriers are generated in the thin active semiconductor layer. As a result, SOI DRAMs are less prone to disturbance of data charges resulting from alpha particles. Thus, storage capacitors in an SOI DRAM can be an estimated one-tenth the size of storage capacitors in a bulk silicon DRAM. The difference may become even greater as technology advances and dimensions become smaller. Bulk silicon DRAMs will require comparatively larger-valued storage capacitances. Such larger storage capacitances will likely occupy more integrated circuit area or require a high dielectric constant insulating material, thereby increasing fabrication cost and complexity. SOI DRAMs, having smaller-valued storage capacitances, will be cheaper than bulk silicon DRAMs.
A further consideration is a body bias voltage that is provided to the body portion of the memory cell access FET to improve memory cell operation. The body bias voltage allows the memory cell to operate from a low power supply voltage, such as 1.5 volts, from which a gate voltage controlling the access FET is derived. Turning the access FET on to transfer data to or from the storage capacitor requires a gate voltage in excess of a turn-on threshold voltage. However, low power supply voltages, such as 1.5 volts, may not provide sufficient overdrive voltage in excess of the threshold voltage to fully turn on the access FET. The gate voltage required for turning on the access FET can be reduced by controlling the body bias voltage. The body bias voltage also controls a subthreshold leakage current of the access FET. The access FET is turned off when data is stored as charge on the storage capacitor. During the time period when the access FET is turned off, the subthreshold leakage current removes some of the stored data charges from the storage node of the storage capacitor. The body bias voltage value controls the reverse bias of the access FET pn junction that is coupled to the storage node.
By increasing the reverse bias of such pn junctions, the subthreshold leakage current is reduced. Without a proper body bias voltage, the subthreshold leakage current would lead to short data retention times.
Providing the body bias voltage to the memory cell access FETs requires a conductive body line that interconnects the access FET body contacts to receive the body bias voltage. The body line, as well as bit line, word line, and other such conductors all occupy integrated circuit surface area. To increase DRAM data storage density, the surface area of each memory cell, referred to as its xe2x80x9cfootprintxe2x80x9d, must be minimized. However, conventional memory cells typically require word lines and body lines on the upper surface of the memory cell, requiring surface area in addition to that of the memory cell storage capacitor.
For the reasons stated above, and for other reasons stated below which will become apparent to those skilled in the art upon reading and understanding the present specification, there is a need in the art for a DRAM or other semiconductor memory device having a memory cell providing an access FET word and body lines that occupy reduced integrated circuit area There is a further need in the art for a compact radiation tolerant memory cell that allows the use of smaller storage capacitors to increase memory data storage density and to reduce integrated circuit manufacturing costs.
The present invention provides a memory cell. A semiconductor island is formed on a substrate. An access transistor is formed in the island, including first and second source/drain regions, a gate region, and a body region. A conductive word line is formed substantially adjacent to the island and located at a height that is no higher than the island""s upper surface. The word line is coupled to the gate region of the access transistor. A conductive body region is formed substantially adjacent to a side surface of the island and located at a height that is no higher than the island""s upper surface. The body line is coupled to the body region of the access transistor. A conductive bit line is electrically coupled to the first source/drain region of the access transistor. A storage capacitor is coupled to the second source/drain region of the access transistor.
In another embodiment, the memory cell array comprises a plurality of memory cells. Each memory cell includes an access transistor having a gate region, body region, and first and second source/drain regions. Each memory cell further includes a storage capacitor coupled to the second source/drain region of the access transistor. A plurality of parallel isolation trenches includes first and second trenches alternatingly disposed between rows of the memory cells for providing isolation therebetween. A plurality of word lines is provided. Each word line is carried in one of the first trenches at a height that is no higher than the upper surface of the body region of the access transistor. Each word line is coupled to the gate region of access transistors in the row of the memory cells. A plurality of body lines is provided. Each body line is carried in one of the second trenches at a height that is no higher than the upper surface of the access transistor. Each body line is coupled to the body region of access transistors in at least one row of the memory cells. A plurality of bit lines is provided. Each bit line is coupled to the first source/drain region of ones of the access transistors.
In another embodiment, the semiconductor memory array includes a dielectric layer carried by a substrate. First and second semiconductor bars are formed on the dielectric layer. Each of the bars includes a plurality of active areas. An electrically isolating dielectric material is interposed between adjacent ones of the active areas. A plurality of access transistors is provided, including an access transistor formed in each of the active areas of the bars. A plurality of isolation trenches is provided, including a trench located between the first and second bars and extending approximately the length of the bar. A plurality of word lines is provided, including a word line located in the trench and extending approximately the length of the trench along a first side of the bars. A plurality of body lines is provided, including a body line extending approximately along a second side of the first and second bars. A plurality of bit lines is also provided.
Another embodiment of the present invention provides a semiconductor memory device, including a memory array. The memory array includes a plurality of bit lines, a plurality of word lines, and a plurality of memory cells. Each memory cell includes an access transistor having a gate region, a body region, and first and second source/drain regions. Each memory cell includes a storage capacitor that is electrically coupled to the second source/drain region of the access transistor. Access circuitry is provided for accessing the memory cells. A plurality of isolation trenches is provided, including a first trench between first and second access transistors and a second trench between the second and third access transistors. A first one of the word lines is located in the first trench at a height that is no higher than the upper surface of the access transistor. The first word line is electrically coupled to the gate regions of the first and second access transistors. A first one of the body lines is located in the second trench at a height that is no higher than the upper surface of the access transistor. The first body line is electrically coupled to the body portions of the second and third access transistors. A first one of the bit lines is coupled to the first source/drain region of each of the first, second and third access transistors.
Another embodiment of the invention includes a method of fabricating a memory array on a semiconductor substrate. First and second trenches are formed in the substrate to define a bar of the semiconductor material. An insulating layer is formed between the bar and the substrate for providing electrical isolation therebetween. A plurality of active areas of semiconductor material are defined on the bar. An access transistor is produced in each of the active areas. Each access transistor includes gate, body, and first and second source/drain regions. A word line is formed in the first trench. The word line is coupled to the gate region of at least one of the access transistors. A body line is formed in the second trench. The body line is electrically connected to the body portion of at least one of the access transistors.
Another embodiment of the invention provides a method for fabricating a memory array on a semiconductor substrate. A plurality of trenches is formed in the substrate to define at least first, second and third bars of the semiconductor material. An insulating layer is formed between the bars and the substrate for providing electrical isolation therebetween. A plurality of semiconductor active areas is defined on each of the bars. An access transistor is produced in each of the active areas. Each access transistor includes gate, body, and first and second source/drain regions. A word line is formed in a first one of the trenches. The word line is coupled to the gate region of a plurality of the access transistors on the first and second bars. A body line is formed in a second one of the trenches. The body line is electrically coupled to the body region of a plurality of the access transistors on the second and third bars.
Thus, the present invention provides a memory device and fabrication method that includes a memory cell having an access FET word lines and body lines that occupy reduced integrated circuit area. The invention also provides a compact radiation insensitive semiconductor-on-insulator memory cell, which uses a smaller storage capacitor, increases memory data storage density, and reduces integrated circuit manufacturing costs.